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________________________________________________________________ _ maxim integrated products _ _ 1 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maxim-ic.com. MAX2064 dual 50mhz to 1000mhz high-linearity, serial/analog-controlled vga 19-5618; rev 0; 12/10 general description the MAX2064 high-linearity, dual analog variable-gain amplifier (vga) operates in the 50mhz to 1000mhz fre - quency range. each analog attenuator is controlled using an external voltage, or through the spi?-compatible interface using an on-chip 8-bit dac. since each of the stages has its own external rf input and rf output, this component can be con - figured to either optimize noise figure (nf) (ampli - fier configured first) or oip3 (amplifier last). the devices performance features include 24db ampli - fier gain (amplifier only), 4.4db nf at maximum gain (includes attenuator insertion losses), and a high oip3 level of +41dbm. each of these features makes the device an ideal vga for multipath receiver and transmitter applications. in addition, the device operates from a single +5v supply with full performance, or a +3.3v supply for an enhanced power-savings mode with lower performance. the device is available in a compact 48-pin tqfn package (7mm x 7mm) with an exposed pad. electrical performance is guaranteed over the extended tempera - ture range, from t c = -40 n c to +85nc. applications if and rf gain stages temperature-compensation circuits wcdma, td-scdma, and cdma2000 m base stations gsm 850/gsm 900 edge base stations wimaxk , lte, and td-lte base stations and customer-premise equipment fixed broadband wireless access wireless local loop military systems features s independently_ controlled_ dual_ paths s 50mhz_ to_ 1000mhz_ rf_ frequency_ range s pin-compatible_ family_ includes max2062_ (analog/digital_ vga)_ max2063_ (digital-only_ vga) s 22db_ (typ)_ maximum_ gain s 0.19db_ gain_ flatness_ over_ 100mhz_ bandwidth s 33db_ gain_ range_ s 49db_ path_ isolation_ (at_ 200mhz) s built-in_ 8-bit_ dacs_ for_ analog_ attenuation_ control s excellent_ linearity_ at_ 200mhz_ (configured_ with_ amp_ last)_ _ +41dbm_ oip3_ _ +59dbm_ oip2_ _ +19dbm_ output_ 1db_ compression_ point s 4.4db_ typical_ noise_ figure_ (at_ 200mhz) s single_ +5v_ supply_ (or_ +3.3v_ operation) s amplifier_ power-down_ mode_ for_ tdd_ applications + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. t = tape and reel. ordering information spi is a trademark of motorola, inc. cdma2000 is a registered trademark of telecommunications industry association. wimax is a trademark of wimax forum. part temp_range pin-package MAX2064etm+ -40nc to +85nc 48 tqfn-ep* MAX2064etm+t -40nc to +85nc 48 tqfn-ep*
2 ______________________________________________________________________________________ MAX2064 dual 50mhz to 1000mhz high-linearity, serial/analog-controlled vga stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v cc_amp_1 , v cc_amp_2 , v cc_rg to gnd .......... -0.3v to +5.5v pd_1, pd_2, ampset to gnd ............................. -0.3v to +3.6v a_vctl_1, a_vctl_2 to gnd ............................. -0.3v to +3.6v dat, cs , clk, aa_sp to gnd ............................ -0.3v to +3.6v amp_in_1, amp_in_2 to gnd .......................... +0.95v to +1.2v amp_out_1, amp_out_2 to gnd ..................... -0.3v to +5.5v a_att_in_1, a_att_in_2, a_att_out_1, a_att_out_2 to gnd ......................................... 0v to +3.6v reg_out to gnd ................................................ -0.3v to +3.6v rf input power (a_att_in_1, a_att_in_2) ................. +20dbm rf input power (amp_in_1, amp_in_2) ....................... +18dbm q jc (notes 1, 2) ......................................................... +12.3nc/w q ja (notes 2, 3) ............................................................ +38nc/w continuous power dissipation (note 1) .............................. 5.3w operating case temperature range (note 4) .. -40n c to +85nc junction temperature ..................................................... +150nc storage temperature range ............................ -65n c to +150nc lead temperature (soldering, 10s) ................................ +300nc soldering temperature (reflow) ...................................... +260nc +5v su ppl y dc electrical characteristics ( typical application circuit , v cc = v cc_amp_1 = v cc_amp_2 = v cc_rg = +4.75v to +5.25v, ampset = 0, pd_1 = pd_2 = 0, t c = -40 n c to +85n c. typical values are at v cc_ = +5.0v and t c = +25 n c, unless otherwise noted.) +3.3v su ppl y dc electrical characteristics ( typical application circuit , v cc = v cc_amp_1 = v cc_amp_2 = v cc_rg = +3.135v to +3.465v, ampset = 1, pd_1 = pd_2 = 0, t c = -40 n c to +85n c. typical values are at v cc_ = +3.3v and t c = +25 n c, unless otherwise noted.) absolu te maximu m ratings note 1: based on junction temperature t j = t c + ( q jc x v cc x i cc ). this formula can be used when the temperature of the exposed pad is known while the device is soldered down to a pcb. see the applications information section for details. the junction temperature must not exceed +150 nc. note 2: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four- layer board. for detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial. note 3: junction temperature t j = t a + ( q ja x v cc x i cc ). this formula can be used when the ambient temperature of the pcb is known. the junction temperature must not exceed +150 nc. note 4: t c is the temperature on the exposed pad of the package. t a is the ambient temperature of the device and pcb. parameter symbol conditions min typ max units supply voltage v cc 4.75 5 5.25 v supply current i dc 143 210 ma power-down current i dcpd pd_1 = pd_2 = 1, v ih = 3.3v 5.3 8 ma input low voltage v il 0.5 v input high voltage v ih 1.7 3.465 v input logic current i ih, i il -1 +1 fa parameter symbol conditions min typ max units supply voltage v cc 3.135 3.3 3.465 v supply current i dc 84.7 145 ma power-down current i dcpd pd_1 = pd_2 = 1, v ih = 3.3v 4.5 8 ma input low voltage v il 0.5 v input high voltage v ih 1.7 v
_______________________________________________________________________________________ 3 MAX2064 dual 50mhz to 1000mhz high-linearity, serial/analog-controlled vga recommended ac operating conditions +5v su ppl y ac electrical characteristics (each path, unless otherwise noted) ( typical application circuit , v cc = v cc_amp_1 = v cc_amp_2 = v cc_rg = +4.75v to +5.25v, attenuators are set for maximum gain, rf ports are driven from 50 i sources, ampset = 0, pd_1 = pd_2 = 0, 100mhz p f rf p 500mhz, t c = -40 n c to +85n c. typical values are at maximum gain setting, v cc = +5.0v, p in = -20dbm, f rf = 350mhz, and t c = +25 n c, unless otherwise noted.) (note 6) parameter symbol conditions min typ max units rf frequency f rf (note 5) 50 1000 mhz parameter symbol conditions min typ max units small-signal gain g f rf = 50mhz 22.4 db f rf = 100mhz 22.3 f rf = 200mhz 22.2 f rf = 350mhz, t c = +25nc 19.5 21.9 23.5 f rf = 450mhz 21.7 f rf = 750mhz 21.4 f rf = 900mhz 20.6 gain vs. temperature -0.006 db/nc gain flatness vs. frequency from 100mhz to 200mhz 0.18 db any 100mhz frequency band from 200mhz to 500mhz 0.19 noise figure nf f rf = 50mhz 4.4 db f rf = 100mhz 4.4 f rf = 200mhz 4.4 f rf = 350mhz 4.6 f rf = 450mhz 4.7 f rf = 750mhz 5.3 f rf = 900mhz 5.7 total attenuation range f rf = 350mhz, t c = +25nc 30 32.9 db output second-order intercept point oip2 p out = 0dbm/tone, df = 1mhz, f 1 + f 2 53.7 dbm path isolation rf input 1 amplified power measured at rf output 2 relative to rf output 1, all unused ports terminated to 50i 48.7 db rf input 2 amplified signal measured at rf output 1 relative to rf output 2, all unused ports terminated to 50i 48.6 output third-order intercept point oip3 p out = 0dbm/tone, d f = 1mhz, f rf = 50mhz 46.3 dbm p out = 0dbm/tone, d f = 1mhz, f rf = 100mhz 44.2 p out = 0dbm/tone, d f = 1mhz, f rf = 200mhz 41.1 p out = 0dbm/tone, d f = 1mhz, f rf = 350mhz 37.1 p out = 0dbm/tone, d f = 1mhz, f rf = 450mhz 34.9 p out = 0dbm/tone, d f = 1mhz, f rf = 750mhz 28.2 p out = 0dbm/tone, d f = 1mhz, f rf = 900mhz 24.6
4 ______________________________________________________________________________________ MAX2064 dual 50mhz to 1000mhz high-linearity, serial/analog-controlled vga +5v su ppl y ac electrical characteristics (each path, unless otherwise noted) (continued) ( typical application circuit , v cc = v cc_amp_1 = v cc_amp_2 = v cc_rg = +4.75v to +5.25v, attenuators are set for maximum gain, rf ports are driven from 50 i sources, ampset = 0, pd_1 = pd_2 = 0, 100mhz p f rf p 500mhz, t c = -40 n c to +85n c. typical values are at maximum gain setting, v cc = +5.0v, p in = -20dbm, f rf = 350mhz, and t c = +25 n c, unless otherwise noted.) (note 6) parameter symbol conditions min typ max units output -1db compression point p 1db f rf = 350mhz, t c = +25nc (note 7) 17 18.7 dbm second harmonic p out = +3dbm -56.7 dbc third harmonic p out = +3dbm -72.4 dbc group delay includes ev kit pcb delays 0.9 ns amplifier power-down time pd_1 or pd_2 from 0 to 1, amplifier dc supply current settles to within 0.1ma 0.5 fs amplifier power-up time pd_1 or pd_2 from 1 to 0, amplifier dc supply current settles to within 1% 0.5 fs input return loss rl in 50i source 16.8 db output return loss rl out 50i load 30.7 db analog attenuator (each path, unless otherwise noted) insertion loss il 2.2 db input second-order intercept point iip2 p in1 = 0dbm, p in2 = 0dbm (minimum attenuation), df = 1mhz, f 1 + f 2 61.9 dbm input third-order intercept point iip3 p in1 = 0dbm, p in2 = 0dbm (minimum attenuation), df = 1mhz 37.0 dbm attenuation range 32.9 db gain control slope analog control input -13.3 db/v maximum gain control slope over analog control input range -35.2 db/v insertion phase change over analog control input range 16.5 deg/v attenuator response time rf settled to within q0.5db 31db to 0db, aa_sp = 0, from a_vctl_ step 500 ns 31db to 0db, aa_sp = 1, from cs step 500 0db to 31db, aa_sp = 0, from a_vctl_ step 500 0db to 31db, aa_sp = 1, from cs step 500 group delay vs. control voltage over analog control input from 0.25v to 2.75v -0.26 ns analog control input range 0.25 2.75 v analog control input impedance 19.2 ki input return loss 50i source 16.0 db output return loss 50i load 15.9 db
_______________________________________________________________________________________ 5 MAX2064 dual 50mhz to 1000mhz high-linearity, serial/analog-controlled vga +5v su ppl y ac electrical characteristics (each path, unless otherwise noted) (continued) ( typical application circuit , v cc = v cc_amp_1 = v cc_amp_2 = v cc_rg = +4.75v to +5.25v, attenuators are set for maximum gain, rf ports are driven from 50 i sources, ampset = 0, pd_1 = pd_2 = 0, 100mhz p f rf p 500mhz, t c = -40 n c to +85n c. typical values are at maximum gain setting, v cc = +5.0v, p in = -20dbm, f rf = 350mhz, and t c = +25 n c, unless otherwise noted.) (note 6) +3.3v su ppl y ac e lectrical c haracteristics (each path, unless otherwise noted) ( typical application circuit , v cc = v cc_amp_1 = v cc_amp_2 = v cc_rg = +3.135v to +3.465v, attenuators are set for maximum gain, rf ports are driven from 50 i sources, ampset = 1, pd_1 = pd_2 = 0, 100mhz p f rf p 500mhz, t c = -40 n c to +85n c. typical values are at maximum gain setting, v cc = +3.3v, p in = -20dbm, f rf = 350mhz, and t c = +25 n c, unless otherwise noted.) (note 6) note 5: operation outside this range is possible, but with degraded performance of some parameters. see the typical operating characteristics. note 6: all limits include external component losses. output measurements are performed at the rf output port of the typical application circuit . note 7: it is advisable not to continuously operate the rf input 1 or rf input 2 above +15dbm. parameter symbol conditions min typ max units d/a converter number of bits 8 bits output voltage dac code = 00000000 0.35 v dac code = 11111111 2.7 serial peripheral interface (spi) maximum clock speed 20 mhz data-to-clock setup time t cs 2 ns data-to-clock hold time t ch 2.5 ns clock-to-cs setup time t es 3 ns cs positive pulse width t ew 7 ns cs setup time t ews 3.5 ns clock pulse width t cw 5 ns parameter symbol conditions min typ max units small-signal gain g 21.8 db output third-order intercept point oip3 p out = 0dbm/tone 29.1 dbm noise figure nf 4.8 db total attenuation range 32.9 db path isolation rf input 1 amplified power measured at rf output 2 relative to rf output 1, all unused ports terminated to 50i 48.1 db rf input 2 amplified signal measured at rf output 1 relative to rf output 2, all unused ports terminated to 50i 48.2 output -1db compression point p 1db (note 7) 13.2 dbm
6 ______________________________________________________________________________________ MAX2064 dual 50mhz to 1000mhz high-linearity, serial/analog-controlled vga typical operating characteristics ( typical application circuit, v cc = v cc_amp_1 = v cc_amp_2 = v cc_rg = +5v , attenuators are set for maximum gain, rf ports are driven from 50i sources, ampset = 0, pd_1 = pd_2 = 0, p in = -20dbm, f rf = 350mhz, and t c = +25nc, unless otherwise noted.) supply current vs. supply votage MAX2064 toc01 v cc (v) supply current (ma) 5.125 5.000 4.875 135 145 155 165 125 4.750 5.250 t c = +85c t c = +25c t c = -40c rf frequency (mhz) gain (db) 850 650 450 250 19 20 21 22 23 24 18 50 1050 gain vs. rf frequency MAX2064 toc02 notch due to self-resonance of bias coil (see table 4) t c = +25c t c = +85c t c = -40c rf frequency (mhz) gain (db) 850 650 450 250 19 20 21 22 23 24 18 50 1050 gain vs. rf frequency MAX2064 toc03 v cc = 4.75v, 5.00v, 5.25v gain over analog attenuator setting vs . rf frequency MAX2064 toc04 rf frequency (mhz) gain over analog attenenuator setting (db) 850 650 250 450 -11 -6 -1 4 14 9 19 24 -16 50 1050 dac code 32 dac code 255 dac code 64 dac code 128 dac code 0 gain vs. analog attenuator setting MAX2064 toc05 analog attenuator setting (dac code) gain (db) 224 192 32 64 96 128 160 -11 -6 -1 4 9 14 19 50mhz 24 -16 0 256 350mhz 200mhz 1000mhz gain vs. analog attenuator setting MAX2064 toc06 analog attenuator setting (dac code) gain (db) 224 192 32 64 96 128 160 -11 -6 -1 4 9 14 19 24 -16 0 256 t c = -40 c, +25 c, +85 c rf = 350mhz gain vs. analog attenuator setting MAX2064 toc07 analog attenuator setting (dac code) gain (db) 224 192 32 64 96 128 160 -11 -6 -1 4 9 14 19 24 -16 0 256 v cc = 4.75v, 5.00v, 5.25v rf = 350mhz input match vs. analog attenuator setting MAX2064 toc08 analog attenuator setting (dac code) input match (db) 224 192 160 128 96 64 32 -30 -25 -20 -15 -10 -5 0 -35 0 256 200mhz 1000mhz 350mhz 50mhz output match vs. analog attenuator setting MAX2064 toc09 analog attenuator setting (dac code) output match (db) 224 192 160 128 96 64 32 -30 -25 -20 -15 -10 -5 0 -35 0 256 1000mhz 50mhz 200mhz 350mhz
_______________________________________________________________________________________ 7 MAX2064 dual 50mhz to 1000mhz high-linearity, serial/analog-controlled vga typical operating characteristics (continued) ( typical application circuit, v cc = v cc_amp_1 = v cc_amp_2 = v cc_rg = +5v , attenuators are set for maximum gain, rf ports are driven from 50i sources, ampset = 0, pd_1 = pd_2 = 0, p in = -20dbm, f rf = 350mhz, and t c = +25nc, unless otherwise noted.) channel?to?channel isolation vs. rf frequency MAX2064 toc10 rf frequency (mhz) channel?to?channel isolation (db) 850 650 450 250 70 60 50 both analog attenuators = code 0 40 30 20 10 80 50 1050 both analog attenuators = code 255 rf frequency (mhz) reverse isolation over analog attenuator setting 850 650 450 250 80 70 60 50 40 30 90 50 1050 reverse isolation over analog attenuator setting vs. rf frequency MAX2064 toc11 dac code 255 dac code 0 s21 phase change vs. analog attenuator setting MAX2064 toc12 analog attenuator setting (dac code) s21 phase change (degrees) 224 192 160 128 96 64 32 -40 -20 0 20 1000mhz 350mhz 50mhz 200mhz 40 60 80 -60 0 256 referenced to high gain state positive phase = electrically shorter rf frequency (mhz) noise figure (db) 850 650 450 250 3 4 5 6 7 8 2 50 1050 noise figure vs. rf frequency MAX2064 toc13 t c = +85c t c = -40c t c = +25c rf frequency (mhz) noise figure (db) 850 650 450 250 3 4 5 6 7 8 2 50 1050 noise figure vs. rf frequency MAX2064 toc14 v cc = 4.75v, 5.00v, 5.25v output p 1db vs. rf frequency MAX2064 toc15 rf frequency (mhz) output p 1db (dbm) 850 650 450 250 13 15 17 19 21 11 50 1050 t c = +85c t c = +25c t c = -40c output p 1db vs. rf frequency MAX2064 toc16 rf frequency (mhz) output p 1db (dbm) 850 650 450 250 13 15 17 19 21 11 50 1050 v cc = 4.75v v cc = 5.00v v cc = 5.25v output ip3 vs. rf frequency MAX2064 toc17 rf frequency (mhz) output ip3 (dbm) 850 650 450 250 25 30 35 40 45 50 20 50 1050 p out = 0db m/ tone t c = +85c t c = +25c t c = -40c output ip3 vs. rf frequency MAX2064 toc18 rf frequency (mhz) output ip3 (dbm) 850 650 450 250 25 30 35 40 45 50 20 50 1050 p out = 0db m/ tone v cc = 5.25v v cc = 4.75v v cc = 5.00v
8 ______________________________________________________________________________________ MAX2064 dual 50mhz to 1000mhz high-linearity, serial/analog-controlled vga typical operating characteristics (continued) ( typical application circuit, v cc = v cc_amp_1 = v cc_amp_2 = v cc_rg = +5v , attenuators are set for maximum gain, rf ports are driven from 50i sources, ampset = 0, pd_1 = pd_2 = 0, p in = -20dbm, f rf = 350mhz, and t c = +25nc, unless otherwise noted.) output ip3 vs. analog attenuator setting MAX2064 toc19 analog attenuator setting (dac code) 224 192 160 128 96 64 32 0 256 p out = -3db m/tone rf = 350mhz output ip3 (dbm) 25 30 35 40 45 50 20 t c = +25c lsb, usb t c = -40c lsb, usb t c = +85c lsb, usb 2nd harmonic vs. rf frequency MAX2064 toc20 2nd harmonic (dbc) 40 50 60 70 30 rf frequency (mhz) 850 650 450 250 50 1050 p out = 3dbm t c = +85c t c = +25c t c = -40c 2nd harmonic vs. rf frequency MAX2064 toc21 2nd harmonic (dbc) 40 50 60 70 30 rf frequency (mhz) 850 650 450 250 50 1050 p out = 3dbm v cc = 5.25v v cc = 5.00v v cc = 4.75v 2nd harmonic vs. analog attenuator setting MAX2064 toc22 2nd harmonic (dbc) 50 55 60 65 70 45 analog attenuator setting (dac code) 224 192 160 128 96 64 32 0 256 p out = 0dbm rf = 350mhz t c = +25c t c = -40c t c = +85c 60 70 80 90 100 50 3rd harmonic vs. rf frequency MAX2064 toc23 3rd harmonic (dbc) rf frequency (mhz) 850 650 450 250 50 1050 p out = 3dbm t c = +25c t c = +85c t c = -40c 3rd harmonic vs. rf frequency 0 MAX2064 toc24 p out = 3dbm 60 70 80 90 100 50 3rd harmonic (dbc) rf frequency (mhz) 850 650 450 250 50 1050 v cc = 5.25v v cc = 4.75v v cc = 5.00v 3rd harmonic vs. analog attenuator setting MAX2064 toc25 3rd harmonic (dbc) 60 70 80 90 50 analog attenuator setting (dac code) 224 192 160 128 96 64 32 0 256 t c = +85c t c = +25c t c = -40c p out = 0dbm rf = 350mhz oip2 vs. rf frequency 0 MAX2064 toc26 p out = 0dbm / tone 30 40 50 60 70 20 oip2 (dbm) rf frequency (mhz) 850 650 450 250 50 1050 t c = -40c t c = +85c t c = +25c oip2 vs. rf frequency 0 MAX2064 toc27 p out = 0db m / tone 60 50 40 70 30 oip2 (dbm) rf frequency (mhz) 850 650 450 250 50 1050 v cc = 4.75v v cc = 5.00v v cc = 5.25v
_______________________________________________________________________________________ 9 MAX2064 dual 50mhz to 1000mhz high-linearity, serial/analog-controlled vga typical operating characteristics (continued) ( typical application circuit, v cc = v cc_amp_1 = v cc_amp_2 = v cc_rg = +5v , attenuators are set for maximum gain, rf ports are driven from 50i sources, ampset = 0, pd_1 = pd_2 = 0, p in = -20dbm, f rf = 350mhz, and t c = +25nc, unless otherwise noted.) oip2 vs. analog attenuator setting MAX2064 toc28 oip2 (dbm) 45 50 55 60 65 40 analog attenuator setting (dac code) 224 192 160 128 96 64 32 0 256 t c = -40c t c = +25c t c = +85c p out = -3db m/ tone rf = 350mhz dac voltage vs. dac code MAX2064 toc29 dac code dac voltage (v) 224 192 160 128 96 64 32 1.5 1.0 2.5 2.0 2.5 3.0 0 0 256 t c = -40c, +25c, +85c dac voltage vs. dac code MAX2064 toc30 dac code dac voltage (v) 224 192 160 128 96 64 32 0.5 1.0 1.5 2.0 2.5 3.0 0 0 256 v cc = 4.75v, 5.00v, 5.25v dac voltage drift vs. dac code MAX2064 toc31 dac code dac voltage drift (v) 224 192 128 160 64 96 32 -0.04 -0.03 -0.02 -0.01 0 0.01 0.02 0.03 0.04 0.05 -0.05 0 256 t c changed from +25c to -40c t c changed from +25c to +85c -0.0075 -0.0050 -0.0025 0 0.0025 0.0050 0.0075 0.0100 -0.0100 dac voltage drift vs. dac code dac voltage drift (v) MAX2064 toc32 dac code 224 192 128 160 64 96 32 0 256 v cc changed from 5.00v to 5.25v v cc changed from 5.00v to 4.75v gain vs. rf frequency (analog attenuator only) MAX2064 toc33 rf frequency (mhz) gain (db) 850 650 450 250 -4 -3 -2 -1 0 -5 50 1050 t c = -40c t c = +85c t c = +25c gain vs. rf frequency (analog attenuator only) MAX2064 toc34 rf frequency (mhz) gain (db) 850 650 450 250 -4 -3 -2 -1 0 -5 50 1050 v cc = 4.75v, 5.00v, 5.25v
10 _____________________________________________________________________________________ MAX2064 dual 50mhz to 1000mhz high-linearity, serial/analog-controlled vga typical operating characteristics ( typical application circuit, v cc = v cc_amp_1 = v cc_amp_2 = v cc_rg = +3.3v , attenuators are set for maximum gain, rf ports are driven from 50i sources, ampset = 1, pd_1 = pd_2 = 0, p in = -20dbm, f rf = 350mhz, and t c = +25nc, unless otherwise noted.) supply current vs. supply voltage MAX2064 toc35 v cc (v) supply current (ma) 3.4 3.3 3.2 70 80 90 100 110 60 3.1 3.5 t c = -40c t c = +85c t c = +25c gain vs. rf frequency MAX2064 toc36 rf frequency (mhz) gain (db) 850 650 450 250 19 20 21 22 23 24 18 50 1050 v cc = 3.3v t c = -40c t c = +85c t c = +25c gain vs. rf frequency MAX2064 toc37 rf frequency (mhz) gain (db) 850 650 450 250 19 20 21 22 23 24 18 50 1050 v cc = 3.30v v cc = 3.135v v cc = 3.465v gain over analog attenuator setting vs. rf frequency MAX2064 toc38 rf frequency (mhz) gain over analog attenuator setting (db) 850 650 250 450 -11 -6 -1 4 14 9 19 24 -16 50 1050 dac code 0 dac code 32 dac code 64 dac code 128 dac code 225 v cc = 3.3v gain vs. analog attenuator setting MAX2064 toc39 analog attenuator setting (dac code) gain (db) 224 192 32 64 96 128 160 0 256 -11 -6 -1 4 14 9 19 24 -16 v cc = 3.3v 50mhz 200mhz 350mhz 1000mhz gain vs. analog attenuator setting MAX2064 toc40 analog attenuator setting (dac code) gain (db) 224 192 32 64 96 128 160 0 256 -11 -6 -1 4 14 9 19 24 -16 v cc = 3.3v rf = 350mhz t c = -40c, +25c, +85c gain vs. analog attenuator setting MAX2064 toc41 analog attenuator setting (dac code) gain (db) 224 192 32 64 96 128 160 0 256 -11 -6 -1 4 14 9 19 24 -16 rf = 350mhz v cc = 3.135v, 3.30v, 3.465v input match vs. analog attenuator setting MAX2064 toc42 analog attenuator setting (dac code) input match (db) 224 192 160 128 96 64 32 -30 -25 -20 -15 -10 -5 0 -35 0 256 v cc = 3.3v 50mhz 200mhz 350mhz 1000mhz output match vs. analog attenuator setting MAX2064 toc43 analog attenuator setting (dac code) output match (db) 224 192 160 128 96 64 32 -30 -25 -20 -15 -10 -5 0 -35 0 256 v cc = 3.3v 50mhz 200mhz 1000mhz 350mhz
______________________________________________________________________________________ 11 MAX2064 dual 50mhz to 1000mhz high-linearity, serial/analog-controlled vga typical operating characteristics (continued) ( typical application circuit, v cc = v cc_amp_1 = v cc_amp_2 = v cc_rg = +3.3v , attenuators are set for maximum gain, rf ports are driven from 50i sources, ampset = 1, pd_1 = pd_2 = 0, p in = -20dbm, f rf = 350mhz, and t c = +25nc, unless otherwise noted.) noise figure vs. rf frequency MAX2064 toc44 rf frequency (mhz) noise figure (db) 850 650 450 250 3 4 5 6 7 8 2 50 1050 t c = -40c t c = +85c t c = +25c v cc = 3.3v noise figure vs. rf frequency MAX2064 toc45 rf frequency (mhz) noise figure (db) 850 650 450 250 3 4 5 6 7 8 2 50 1050 v cc = 3.135v v cc = 3.465v v cc = 3.30v output p 1db vs. rf frequency MAX2064 toc46 rf frequency (mhz) output p 1db (dbm) 850 650 450 250 6 8 10 12 14 16 4 50 1050 v cc = 3.3v t c = -40c t c = +85c t c = +25c output p 1db vs. rf frequency MAX2064 toc47 rf frequency (mhz) output p 1db (dbm) 850 650 450 250 6 8 10 12 14 16 4 50 1050 v cc = 3.465v v cc = 3.30v v cc = 3.135v output ip3 vs. rf frequency MAX2064 toc48 rf frequency (mhz) output ip3 (dbm) 850 650 450 250 15 20 25 30 35 40 10 50 1050 p out = 0dbm/ tone v cc = 3.3v t c = -40c t c = +85c t c = +25c output ip3 vs. rf frequency MAX2064 toc49 rf frequency (mhz) output ip3 (dbm) 850 650 450 250 15 20 25 30 35 40 10 50 1050 p out = 0dbm/tone v cc = 3.465v v cc = 3.30v v cc = 3.135v output ip3 vs. analog attenuator setting MAX2064 toc50 analog attenuator setting (dac code) output ip3 (dbm) 224 192 160 128 96 64 32 25 30 35 40 20 0 256 p out = -3dbm/tone v cc = 3.3v rf = 350mhz t c = -40c lsb, usb t c = +25c lsb, usb t c = +85c lsb, usb 2nd harmonic vs. rf frequency MAX2064 toc51 rf frequency (mhz) 2nd harmonic (dbc) 850 650 450 250 25 35 45 55 65 75 15 50 1050 p out = 3dbm v cc = 3.3v t c = +25c t c = +85c t c = -40c 2nd harmonic vs. rf frequency MAX2064 toc52 rf frequency (mhz) 2nd harmonic (dbc) 850 650 450 250 25 35 45 55 65 75 15 50 1050 p out = 3dbm v cc = 3.30v v cc = 3.465v v cc = 3.135v
12 _____________________________________________________________________________________ MAX2064 dual 50mhz to 1000mhz high-linearity, serial/analog-controlled vga typical operating characteristics (continued) ( typical application circuit, v cc = v cc_amp_1 = v cc_amp_2 = v cc_rg = +3.3v , attenuators are set for maximum gain, rf ports are driven from 50i sources, ampset = 1, pd_1 = pd_2 = 0, p in = -20dbm, f rf = 350mhz, and t c = +25nc, unless otherwise noted.) 2nd harmonic vs. analog attenuator setting MAX2064 toc53 analog attenuator setting (dac code) 2nd harmonic (dbc) 224 192 160 128 96 64 32 45 50 55 60 40 0 256 p out = 0dbm v cc = 3.3v rf = 350mhz t c = +85c t c = +25c t c = -40c 3rd harmonic vs. rf frequency MAX2064 toc54 rf frequency (mhz) 3rd harmonic (dbc) 850 650 450 250 40 50 60 70 80 30 50 1050 p out = 3dbm v cc = 3.3v t c = -40c t c = +25c t c = +85c 3rd harmonic vs. rf frequency MAX2064 toc55 rf frequency (mhz) 3rd harmonic (dbc) 850 650 450 250 40 50 60 70 80 30 50 1050 p out = 3dbm v cc = 3.30v v cc = 3.465v v cc = 3.135v 3rd harmonic vs. analog attenuator setting MAX2064 toc56 analog attenuator setting (dac code) 3rd harmonic (dbc) 55 60 65 70 75 50 224 192 160 128 96 64 32 0 256 p out = 0dbm v cc = 3.3v rf = 350mhz t c = -40c t c = +25c t c = +85c oip2 vs. rf frequency MAX2064 toc57 rf frequency (mhz) oip2 (dbm) 850 650 450 250 30 40 50 60 70 20 50 1050 p out = 0dbm/tone v cc = 3.3v t c = +25c t c = +85c t c = -40c oip2 vs. rf frequency MAX2064 toc58 rf frequency (mhz) oip2 (dbm) 850 650 450 250 30 40 50 60 70 20 50 1050 p out = 0dbm/tone v cc = 3.465v v cc = 3.30v v cc = 3.135v oip2 vs. analog attenuator setting MAX2064 toc59 analog attenuator setting (dac code) oip2 (dbm) 224 192 160 128 96 64 32 40 50 60 30 0 256 p out = -3dbm/tone v cc = 3.3v rf = 350mhz t c = +85c t c = +25c t c = -40c
______________________________________________________________________________________ 13 MAX2064 dual 50mhz to 1000mhz high-linearity, serial/analog-controlled vga pin configuration pin description top view MAX2064 tqfn + 13 14 15 16 17 18 19 20 21 22 23 24 gnd gnd gnd gnd gnd gnd gnd a_att_in_2 gnd a_vctl_2 a_att_out_2 v cc_amp_2 48 47 46 45 44 43 42 41 40 39 38 37 1 2 3 4 5 6 7 8 9 10 11 12 ep gnd gnd gnd gnd gnd gnd gnd a_att_in_1 aa_sp a_vctl_1 a_att_out_1 v cc_amp_1 gnd gnd gnd gnd v cc_rg clk dat gnd gnd gnd gnd 36 35 34 33 32 31 30 29 28 27 26 25 gnd amp_in_2 pd_2 gnd amp_out_2 reg_out ampset amp_out_1 gnd pd_1 amp_in_1 gnd cs pin name function 1C4, 9C19, 21, 25, 28, 33, 36, 42C48 gnd ground 5 dat spi data digital input 6 clk spi clock digital input 7 cs spi chip-select digital input 8 v cc_rg regulator supply input. connect to a 3.3v or 5v external power supply. v cc_rg powers all circuits except for the driver amplifiers. bypass with a 10nf capacitor as close as possible to the pin. 20 a_att_in_2 analog attenuator input (50i), path 2. requires a 1000pf dc-blocking capacitor. 22 a_vctl_2 analog attenuator voltage-control input, path 2. bypass to ground with a 150pf capacitor if dac 2 is used (aa_sp = 1). 23 a_att_out_2 analog attenuator output (50i), path 2. requires a dc-blocking capacitor. connect to amp_in_2 through a 1000pf capacitor. 24 v cc_amp_2 driver amplifier supply-voltage input, path 2. bypass with a 10nf capacitor as close as possible to the pin. 26 amp_in_2 driver amplifier input (50i), path 2. requires a dc-blocking capacitor. connect to a_att_out_2 through a 1000pf capacitor. 27 pd_2 power-down, path 2. see table 2 for operation details. 29 amp_out_2 driver amplifier output (50i), path 2. connect a pullup inductor from amp_out_2 to v cc_.
14 _____________________________________________________________________________________ MAX2064 dual 50mhz to 1000mhz high-linearity, serial/analog-controlled vga pin description (continued) detailed description the MAX2064 high-linearity analog vga is a gener - al-purpose, high-performance amplifier designed to interface with 50 i systems operating in the 50mhz to 1000mhz frequency range. each channel of the device integrates an analog attenua - tor to provide 33db of total gain control, as well as a driver amplifier optimized to provide high gain, high ip3, low nf, and low power consumption. each analog attenuator is controlled using an external voltage or through the spi-compatible interface using an on-chip 8-bit dac. see the applications information section and table 3 for attenuator programming details. because each of the two stages in the separate signal paths has its own rf input and rf output, this compo - nent can be configured to either optimize nf (amplifier configured first) or oip3 (amplifier last). the devices per - formance features include 24db amplifier gain (amplifier only), 4.4db nf at maximum gain (includes attenuator insertion losses), and a high oip3 level of +41dbm. each of these features makes the device an ideal vga for mul - tipath receiver and transmitter applications. in addition, the device operates from a single +5v supply with full performance, or a +3.3v supply for an enhanced power-savings mode with lower performance. the device is available in a compact 48-pin tqfn pack - age (7mm x 7mm) with an exposed pad. electrical per - formance is guaranteed over the extended temperature range, from t c = -40 n c to +85nc. analog attenuator control the device integrates two analog attenuators. each analog attenuator has a 33db range and is controlled using an external voltage, or through the 3-wire spi inter - face using an on-chip 8-bit dac. see the applications information section and table 3 for attenuator program- ming details. the attenuators can be used for both static and dynamic power control. note that when the analog attenuators are controlled by the dacs through the spi bus, the dac output voltage shows on a_vctl_1 and a_vctl_2 (pins 39 and 22, respective - ly). therefore, in spi mode, the a_vctl_1 and a_vctl_2 pins must only connect to the resistor and capacitor to ground, as shown in the typical application circuit . pin name function 30 reg_out regulator output. bypass with 1ff capacitor. 31 ampset driver amplifier bias setting for 3.3v operation. set to logic 1 for 3.3v operation on pins v cc_amp_1 and v cc_amp_2 . set to logic 0 for 5v operation. 32 amp_out_1 driver amplifier output (50i), path 1. connect a pullup inductor from amp_out_1 to v cc_. 34 pd_1 power-down, path 1. see table 2 for operation details. 35 amp_in_1 driver amplifier input (50i), path 1. requires a dc-blocking capacitor. connect to a_att_out_1 through a 1000pf capacitor. 37 v cc_amp_1 driver amplifier supply voltage input, path 1. bypass with a 10nf capacitor as close as possible to the pin. 38 a_att_out_1 analog attenuator output (50i), path 1. requires a dc-blocking capacitor. connect to amp_in_1 through a 1000pf capacitor. 39 a_vctl_1 analog attenuator voltage-control input, path 1. bypass to ground with a 150pf capacitor if on-chip dac is used (aa_sp = 1). 40 aa_sp dac enable/disable logic input for analog attenuators. set aa_sp to logic 1 to enable on-chip dac circuit and digital spi control. set aa_sp to logic 0 to disable dac circuit and digital spi control. when aa_sp = 0, use analog control lines (a_vctl_1 and a_vctl_2). 41 a_att_in_1 analog attenuator input (50i), path 1. requires a 1000pf dc-blocking capacitor. ep exposed pad. internally connected to gnd. connect to a large pcb ground plane for proper rf performance and enhanced thermal dissipation.
______________________________________________________________________________________ 15 MAX2064 dual 50mhz to 1000mhz high-linearity, serial/analog-controlled vga table 1. control logic driver amplifier each path of the device includes a high-performance driver with a fixed gain of 24db. the driver amplifier circuits are optimized for high linearity for the 50mhz to 1000mhz frequency range. applications information operating modes the device features an optional +3.3v supply volt - age operation with reduced linearity performance. the ampset pin needs to be biased accordingly in each mode, as listed in table 2. in addition, the driver amplifiers can be shut down independently to conserve dc power. see the biasing scheme outlined in table 2 for details. spi interface and attenuator settings the attenuators can be programmed through the 3-wire spi/microwire k -compatible serial interface using 5-bit words. fifty-six bits of data are shifted in msb first and are framed by cs . the first 28 bits set the first atten- uator and the following 28 bits set the second attenuator. when cs is low, the clock is active and data is shifted on the rising edge of the clock. when cs transitions high, the data is latched and the attenuator setting changes (figure 1). see table 3 for details on the spi data format. table 2. operating modes microwire is a trademark of national semiconductor corp. figure 1. spi timing diagram result v cc (v) amp_set pd_1 pd_2 all on 5 0 0 0 3.3 1 0 0 amp1 off amp2 on 5 0 1 0 3.3 1 1 0 amp1 on amp2 off 5 0 0 1 3.3 1 0 1 all off 5 0 1 1 3.3 1 1 1 aa_sp analog attenuator d/a converter 0 controlled by external control voltage disabled 1 controlled by on-chip dac enabled (dac output voltage shows on a_vctl__ pins); dac uses on-chip voltage reference t cs msb lsb dn d1 d0 d(n-1) t ch t cw t es t ew t ews dat clk cs data entered on clock rising edge. attenuator register state change on cs rising edge. n = number of data bits. d0 is an address bit, d1/dn are data bits (where n p 20). notes:
16 _____________________________________________________________________________________ MAX2064 dual 50mhz to 1000mhz high-linearity, serial/analog-controlled vga table 3. spi data format function bit description reserved d55 (msb) bits d[55:36] are reserved. set to logic 0. d54 d53 d52 d51 d50 d49 d48 d47 d46 d45 d44 d43 d42 d41 d40 d39 d38 d37 d36 on-chip dac (path 2) d35 bit 7 (msb) of on-chip dac used to program the path 2 analog attenuator d34 bit 6 of dac d33 bit 5 of dac d32 bit 4 of dac d31 bit 3 of dac d30 bit 2 of dac d29 bit 1 of dac d28 bit 0 (lsb) of dac
______________________________________________________________________________________ 17 MAX2064 dual 50mhz to 1000mhz high-linearity, serial/analog-controlled vga table 3. spi data format (continued) function bit description reserved d27 bits d[27:8] are reserved. set to logic 0. d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 on-chip dac (path 1) d7 bit 7 (msb) of on-chip dac used to program the path 1 analog attenuator d6 bit 6 of dac d5 bit 5 of dac d4 bit 4 of dac d3 bit 3 of dac d2 bit 2 of dac d1 bit 1 of dac d0 (lsb) bit 0 (lsb) of dac
18 _____________________________________________________________________________________ MAX2064 dual 50mhz to 1000mhz high-linearity, serial/analog-controlled vga power-supply sequencing the sequence to be used is: 1) power supply 2) control lines layout considerations the pin configuration of the device is optimized to facili - tate a very compact physical layout of the device and its associated discrete components. the exposed pad (ep) of the devices 48-pin tqfn-ep package provides a low thermal-resistance path to the die. it is important that the pcb on which the device is mounted be designed to conduct heat from the ep. in addition, provide the ep with a low inductance path to electrical ground. the ep m u st be soldered to a ground plane on the pcb, either directly or through an array of plated via holes. the lay - out of the pcb should include proper top-layer ground shielding to isolate the amplifiers inputs and outputs from each other. shielding between the paths (inputs and outputs) is important for channel-to-channel isolation. table 4. typical application circuit component values * select the inductors to ensure that self-resonance of the inductors is outside the band of operation. designation qty description component supplier c1, c5, c6, c8, c12, c13 6 1000pf ceramic capacitors (0402) grm1555c1h102j murata electronics north america, inc. c3, c10 2 150pf ceramic capacitors (0402) grm1555c1h151j murata electronics north america, inc. c4, c7, c11, c14, c16 5 10nf ceramic capacitors (0402) grm155r71e103k murata electronics north america, inc. c15 1 1ff ceramic capacitor (0603) grm188r71c105k murata electronics north america, inc. l1, l2* 2 820nh inductors (1008) coilcraft 1008cs-821xjlc coilcraft, inc. r1, r2 2 47.5ki resistors (0402) u1 1 48 tqfn-ep (7mm x 7mm) maxim MAX2064etm+ maxim integrated products, inc.
______________________________________________________________________________________ 19 MAX2064 dual 50mhz to 1000mhz high-linearity, serial/analog-controlled vga typical application circuit chip information process: sige bicmos package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern n o. 48 tqfn-ep t4877+7 21-0144 90-0133 13 14 15 16 17 18 19 20 21 22 23 24 gnd gnd gnd gnd gnd gnd gnd a_att_in_2 gnd a_vctl_2 c10 c12 c5 c11 c4 v cc c7 c15 rf output 1 r2 a_att_out_2 v cc_amp_2 48 47 46 45 44 43 42 41 40 39 38 37 1 2 3 4 5 6 7 8 9 10 11 12 gnd gnd gnd gnd gnd gnd gnd a_att_in_1 aa_sp a_vctl_1 a_att_out_1 v cc_amp_1 gnd gnd gnd gnd v cc_rg clk dat gnd gnd gnd gnd gnd amp_in_2 pd_2 gnd amp_out_2 reg_out ampset amp_out_1 gnd pd_1 amp_in_1 gnd 28 26 25 27 29 30 33 31 32 34 35 36 cs analog attenuator 1 analog attenuator 2 spi active bias active bias amp1 amp2 exposed pad c6 c14 rf output 2 c13 v cc v cc c16 v cc + c3 l1 l2 analog attenuator control 2 analog attenuator control 1 rf input1 rf input2 r1 c1 c8 dac dac MAX2064
maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 20 maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2010 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. MAX2064 dual 50mhz to 1000mhz high-linearity, serial/analog-controlled vga revision history revision number revision date description pages changed 0 12/10 initial release

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